if statement in Case - VHDL

I've a problem on how correctly use If statements in Cases.

For example:

case Counter is 
 when 0 =>
     if Signal_1 = '1' and Signal_2 = '1' then
          Output <= '1';
     elsif Signal_1 = '1' and Signal_2 = '0' then
          Counter <= Counter + 1;
     end if;
 when 1 =>
     ..

My error is, when (Signal_1 = '1' and Signal_2 = '1') Output goes correctly to 1 but after some time when (Signal_1 = '1' and Signal_2 = '0') Output goes to 0 and Counter goes +1. Why is that? Should I define Output state in every If statement and in every Counter case?

Also, should I specify all combination of Signal I have or just combinations that I use?

And how should I terminate If statement? Something like this:

case Counter is 
 when 0 =>
     if Signal_1 = '1' and Signal_2 = '1' then
          Output <= '1';
     elsif Signal_1 = '1' and Signal_2 = '0' then
          Counter <= Counter + 1;
     else
          null;
     end if;
     null;
 when 1 =>
     ..