Parking lot VHDL throws syntax error at if statement

A parking lot, shown in the Fig. 2, has space for 10 cars. There is only one entrance to the parking lot, consequently one car at a time can enter or exit the parking. There are two light sensors, separated by one meter in order to detect if the car is entering or leaving the lot. There is a semaphore with signs saying FREE and FULL. Create, simulate and sinthesize a VHDL description to correctly command the lights according to the occupancy of the parking lot.

I have a problem compiling the code when use statement if

VHDL CODE:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity parking_lot is
port (detector_1 : in std_logic; -- entrando carro
        detector_2 : in std_logic; -- saliendo carro
        clk : in std_logic;
        reset : in std_logic;
        modo : in std_logic;
        libre : out std_logic;
        lleno : out std_logic;
        q : out std_logic
        );
end parking_lot;

architecture behavioral of parking_lot is
  signal tmp: std_logic_vector(3 downto 0);
   begin 
    process (clk, reset)
      variable i : integer := 0;
        begin
        if (reset='1') then
          tmp <= "0000";
        elsif (clk'event and clk='1') then
                for i in 0 to 10 loop
                    if (modo='1') then
                        tmp <= tmp + 1;
                    if (modo='0') then
                        tmp <= tmp - 1;
                    end loop;
            end if;
        end process;
    q <= tmp;     
end behavioral;

Error (10500): VHDL syntax error at parking_lot.vhd(31) near text "loop";  expecting "if"
Error (10500): VHDL syntax error at parking_lot.vhd(35) near text "behavioral";  expecting "loop"