VHDL coding error "Else clause after check for clock not supported"

I'm trying to make a counter that sends out a carry signal after every 64 clock pulses. When i try to synthesize the code shown (in Vivado) I get an error

"Else clause after check for clock not supported"

On the line signaled with the '!!'

I do something very similar in a different project and I did not get any errors there, so I don't really get whats wrong. any help?

entity refresh_counter is
     port( CLK : in STD_LOGIC;
           CLR : in STD_LOGIC;
           CARRY : out STD_LOGIC);
end refresh_counter;

architecture Behavioral of refresh_counter is
begin

process(CLK)
variable tel : integer;
begin
    if (CLK'event and CLK = '1') then
        if CLR = '1' then
            tel := 0;
        end if;
    else
        if (tel < 63) then            !!
            tel := tel + 1;
        else
            CARRY <= '1';
            tel := 0;
        end if;
    end if;

end process;
end Behavioral;