Specify default value to variables in verilog always

I have a rather large if else block.

always @(posedge clk)
begin
r<=3;
if(cond1)
a<=1;
else if(cond2)
begin
a<=2;
r<=3;
end
else
a<=3;
end

In this case I am trying to specify a default value for r in the blocks. Would the top r<= statemen be executed for the first and last if blocks?