VHDL if-else condition order

Any idea what is the difference betweet this:

p_persist_reg_CRC_calc: process (Clk_50Mhz)
begin
    if falling_edge(Clk_50Mhz) then
        if crc_rx_init <= '0' then
            flash_crc_calc <= (others =>'1');
            else
            flash_crc_calc <= (others =>'0');
        end if;
    end if;
end process p_persist_reg_CRC_calc;

and this:

p_persist_reg_CRC_calc: process (Clk_50Mhz)
begin
    if falling_edge(Clk_50Mhz) then
        if crc_rx_init <= '1' then
            flash_crc_calc <= (others =>'0');
            else
            flash_crc_calc <= (others =>'1');
        end if;
    end if;
end process p_persist_reg_CRC_calc;

The second stack to zero. In my understanding they should be the same as function. Regards, Emil