I quiete need some help in attempting to create a very specific signal in my code. Basically i need a signal to be generated after load_0 ends, in the falling edge, where such signal would be 10 pulses of the 1KHz signal and the rest 0. Which is just preserving 10 pulses that are aligned with the variable Serial_out.
Thus far i have tried and if to attempt this, with a counter to attempt to count to 10 for the 10 pulses i want and discarding the rest. This always ends either not being able to be synthesized due to error or the test bench clk_trig never being initialized.
My coding is quite cruse due to the fact that i have been using xilinx for about 2 weeks now. Any quick help with examples and such would be greatly appreciated as the deadline ks basically in 4 days.
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