If statement in a for loop VHDL

I want to do a for loop for 8 inputs and an if statement.My purpose is to find minimum of these 8 portsI know what the error is but i want to make (Ι-1) when the (i) take the value of 7.Any ideas? if (a_unss(i)

LIBRARY ieee;
USE ieee.std_logic_1164 .all;
USe ieee.numeric_std .all;
---------------------------------------

ENTITY bitmin IS
generic
(     
size: integer            :=8

);
PORT
(
        A0,A1,A2,A3,A4,A5,A6,A7 : IN UNSIGNED (size-1 downto 0);

        MinOut:out  UNSIGNED (size-1 downto 0)
);     
END Entity;
-------------------------------------------------------------------------


ARCHITECTURE compare OF bitmin IS

type a_uns is array (0 to 7) of unsigned(7 downto 0);
signal a_unss:a_uns;



begin
        a_unss(0)<=(A0);
        a_unss(1)<=(A1);
        a_unss(2)<=(A2);
        a_unss(3)<=(A3);
        a_unss(4)<=(A4);
        a_unss(5)<=(A5);
        a_unss(6)<=(A6);
        a_unss(7)<=(A7);

process(a_unss) 


begin
MinOut<="00000000";
for i in 0 to 7 loop



              if (a_unss(i)<a_unss(i+1))and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1))and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1)) and (a_unss(i)<a_unss(i+1)) then
                     MinOut<=a_unss(i);


        end if;
    end loop;
end process;
END compare;

Error:

Error (10385): VHDL error at bitmin.vhd(48): index value 8 is outside the range (0 to 7) of object "a_unss"

Error (10658): VHDL Operator error at bitmin.vhd(48): failed to evaluate call to operator ""<""
Error (10658): VHDL Operator error at bitmin.vhd(48): failed to evaluate call to operator ""and""
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 4 errors, 1 warning
Error: Peak virtual memory: 4826 megabytes
Error: Processing ended: Thu Apr 09 19:39:04 2020
Error: Elapsed time: 0`enter code here`0:00:17
Error: Total CPU time (on all processors): 00:00:43