How to check wires in if in Verilog?

it looks like my code never enters the if's when I run it on the device. However, it works in simulation. I'm pretty sure the problem is in the if because if I assign the reg1-reg5 without if's the code works fine

module  myTest (
    select, 
    i_sys_clk
);

input           i_sys_clk;      //System clock input

input wire [15:0]   select;
wire            i_sys_clk;

reg [15:0] reg1;
reg [16:0] reg2;
reg [16:0] reg3; 
reg [16:0] reg4;
reg [16:0] reg5;

always @(posedge i_sys_clk) begin

    reg1        = 16'b0000111110110000;

    if (select[15:12]==4h'hA)begin
        reg4        = 17'h1D4C0; 
        reg5        = 17'h1D4B0;
    end

    else if (select[15:12]==4'hB) begin     
        reg4        = 17'd92308;    
        reg5        = 17'd92292;
    end
    
    
    if (select[11:8]==4'hA)begin
        reg2        = 17'h158;      
        reg3        = 17'h168;      
    end
    
    else if (select[11:8]==4'hB) begin      
        reg2        = 17'h2C0;      
        reg3        = 17'h2D0;  
    end
    
end

[...]
endmodule