How to Check Values in a Module vs the Values in Another Module in Verilog

I have this assignment where I am supposed to design an 8 bit 1's complement subtractor that doesn't use word-level operators like + or - and I think that it is working(tested it manually on other values), but the last part of the assignment is to have the testbench iterate all the possible values and add them together(256*256 or 65,536 possible values)(not all the numbers added cumulatively to produce a very large number, but 0+1, 0+2, ... 1+1, 1+2, etc.) and check the calculated values with my other module and print the number of values that match the subtractor correctly and the number of values that are incorrect. The last line of code should look like this:

$display("All cases tested; %d correct, %d failed", correct, failed);

I am not sure what is wrong. This is the error I received:

/home/kaos/IVER/5f5bc293461b.v:115: syntax error
/home/kaos/IVER/5f5bc293461b.v:115: error: invalid module item.
The compiler did not generate a VVP file, so simulation could not be executed.

Here is what I have:

module testbench;
  
  reg [7:0] A;
  reg [7:0] B;
  reg       mode;
  wire [7:0] subtractionresult;
  wire carryoverflow;
  
  refonesub sub( 
    .A(A),
    .B(B),
    .mode(mode),
    .subtractionresult(subtractionresult),
    .carryoverflow(carryoverflow) );
  
 integer i, j;
    initial begin
        for (A = 0; i < 256; A = A + 1) 
                begin
                for (B = 0; B < 256; B = B + 1) 
                begin
                subtractionresult = A+B;
                if (refonesub.subtractionresult == testbench.subtractionresult) begin
                i = i + 1;
                end
                else begin
                j = j + 1;
                end
                end
                end
                end
   $display("All cases tested; %d correct, %d failed", i, j);
  
endmodule