Looking for help in correcting the syntax error in my Verilog code

module HazardDetectionUnit(stall, Rs1, Rt1, Rt2, MemRead2, clk); input clk, MemRead2;

input [4:0] Rs1, Rt1, Rt2;

output reg [2:0] stall;

always @(negedge clk)

begin

if(MemRead2 & ((Rt2 = Rs1) | (Rt2 = Rt1)))  //Error has been detected in this line

  stall <= 3'b000;

else

  stall <= 3'b111;

end

endmodule

ERROR: /nfs/home/s/s_ankith/HazardDetectionUnit_MIPS.v(7): near ")": Syntax error. Assignment sub-exprs. are only allowed in SystemVerilog or PSL.