Verilog - If Condition

I am having an issue with this module in Verilog when compiling on Quartus Prime V16.0. The objective is to return a output a specific 8-bit number [00011000] if any single bit out of 8 total input bits is a 1. Does this if statement work? If not, what is a better method of implementation? Does the operator work this way in returning a 1? From what I've researched it does.

The inputs to the or operator are 4-bit A (in[7:4]) and 4-bit B (in[3:0])

module case3 (in, out);

input [7:0] in;
output [7:0] out;
wire x, y;

assign x = 1;

if (x == or(y, in[7:4], in[3:0]))
    assign out[7:0] = 8'b00011000;

endmodule

The function call in my main module looks like this:

case3 u3(
    .in(SW[7:0]),
    .out(wire3)
);

Wire3 is a wire variable defined to retrieve the output from the Case3 module for further usage.