Verilog: Why is there a if(0) if if(1) is always true?

I have the verilog always block as below:

always @ (a)

begin

if(1) begin .. end

if(0) begin .. end.

end

Does if(1) mean that this statement is executed all the time once the always block is triggered? Then what is the point having if(0)? When is it executed?

Note: This is a legacy code, I'm not the owner of it.

Please help.