Change variable name on the fly in system verilog

I was wondering if system verilog has an ability to change the variable names on the fly. For example, I have the following code :

var1 = 1;
var2 = 2;
var3 = 3;

and I want to do the following checks

if(var1 == 1)
  $display("var1 matched");
if(var2 == 2)
    $display("var2 matched");
if(var3 == 3)
  $display("var3 matched");

So in the above case, if I have 'n' variables, I'll have 'n' checks.

So for this reason, I was looking for an alternative way which works something like this :

for(int i=0; i<=3;i++)
  if($sformatf("var%0d", i) == i) //here the variable name changes on the fly
    $display("var%0d matched", i);

I tried the above code and there were no errors but it wasn't behaving as expected.

I also tried a string concatenation like so

for(int i=0; i<=3;i++)
  if({var,$sformatf("%0d", i)} == i) 
    $display("var%0d matched", i);

Surprisingly this gave no errors too. But it was comparing i to i hence always passes.

Can someone tell me if there is anything in system verilog that I could use?

Thanks