Workaround for systemverilog there is no `if compiler directive

In systemverilog there is no `if compiler directive. So the following lines are incorrect:

`define BITS 16

reg[`BITS-1:0] my_reg;

...
`if `BITS > 10
   my_reg[31] = 1'b0;
endif
...

Without `if there are warnings/errors.

How can I workaround or solve this?