Verlog delays modeling

Example code below.

I have always with if\else. Each portion has its own delay - X\Y. My problem is whether circuit enters the 'if' and start to calculate 'X' delay and then asynchronous event enters 'else' it still remembers the 'X' delay instead of calculate 'Y' delay. ['X' >> 'Y'] The 'if' and 'else' portions working on the same signals [sigA below].

My question, how to verify the asynchronous event clears delay 'X' and starts the 'else' operation from delay 'Y'? Tried also blocking assigments and another hardware tricks [MUX at the out]. But simulator only remembers the long delay. I am trying to avoid overkill design such a logic always [always *] and a counting state machine but using the delay operator.

Thanks.

always @(event) begin if (event) /#X; sigA <= value1; end //end if else begin /#Y; sigA <= value2; end //else end //always