Creating periodic pulse, verilog

I am not an experienced hdl coder. I wanted to write a verilog code that generates periodic pulse with defined high and low state. The output signal should be low during the first 10 clock cycles, high during the next 100 clock cycles, and low for 20 more clock cycles when signal_x is high (clock frequency is 50MHz).

    module produce_pulse(clk, signal_x, pulse);
input clk, signal_x;
output reg pulse;
reg [7:0] j;
initial begin 
j<=0;
end 
always@(posedge clk)
begin 
    if(signal_x) begin 

            if (j<10) // meaning the signal is zero at first 10 clock cycles (200ns) 
                begin
                    pulse<=0;
                    j<=j+1;
                end
            else if((j>=10)&&(j<110)) //pulse is HIGH at next 100 clock cycles (2us) 
                begin 
                    pulse<=1;
                    j<=j+1;
                end 
            else if((j>=110)&&(j<130)) //pulse is LOW at next 20 clock cycles (400ns)
                begin
                    pulse<=0;
                    j<=j+1;
                end 
            else if(j==130) //to end the previous j case appropriately
                begin
                    pulse<=0;
                    j<=0;
                end
    end 
    else 
        pulse<=0;
end 
endmodule 

The code looks like good, but when I simulate I am getting pulses with slightly different high and low state durations and the period is not 2.6us even not a constant number (switches between 2.74us and 2.72us). What might be the reason?