Why do these two seemingly equivalent Boolean expressions evaluate differently in Verilog?

I was debugging some verilog I was writing, and I was only about to get the expected behavior with the following if statement:

if (((a[0]== 1)&&(b[0]==1))||((a[1]==1)&&(b[1]==1))||((a[2]==1&&(b[2]==1))||((a[3]==1)&&(b[3]==1))) begin

Whereas the seemingly equivalent expressions:

if(a&b!=4'b0000) begin

if(!(a&b==4'b0000) begin

if(a&b!=0) begin

if(!(a&b==0) begin

all produce unexpected behavior.

Both a and b are defined as follows:

input [3:0] mm;
input [3:0] stat;

What is happening here? Am I missing something obvious?