If-statements in VHDL: nested vs. multiple conditions

here is what my code somewhat looks like... (I know it does't compile, it's just pseudo code.)

signal  lowBound        :   std_logic_vector(15 downto 0);
signal  highBound       :   std_logic_vector(15 downto 0);
signal  result_01       :   std_logic_vector(15 downto 0);
signal  result_02       :   std_logic_vector(15 downto 0);
signal  result_03       :   std_logic_vector(15 downto 0);


p_state_machine: process(RESET, CLK)
    if (RESET = '1') then
        ...
    elsif (rising_edge(CLK_I)) then
        case currentState is
            when ...
            ...
            when OUTPUT =>
                -- check if results are within interval bounds
                -- option 1
                if ((result_01 > lowBound) AND (result_02 > lowBound) AND (result_03 > lowBound) AND ...) then
                    ...
                end if

                -- option 2
                if ((result_01 > lowBound) then
                    if ((result_02 > lowBound) then
                        if ((result_03 > lowBound) then
                            ...
                        end if;
                    end if;
                end if;
        end case;
    end if;
end process;

As you can see, I have a state machine and would like to output results 1-3 in the last state 'OUTPUT' but only if they are within the given interval bounds. So now I have 6 conditions that I need to check. If all are true I output results 1-3; if at least one is false, I want to set an error flag.

I am working with a Xilinx board at 25MHz but would like to have a robust design that could handle higher frequencies as well.

So now my question(s)... What's the best way to check if results 1-3 are within the given bounds? I know there are multiple options but which one is the best, especially when considering timing? Do options 1 and 2 from my code translate to the same hardware or is there a differnce? Is it better for me to check these conditions outside the state machine in seperate (parallel) processes since I am dealing with 16-bit vectors? (I imagine having 6 nested 16-bit comparisons migth result in timing issues!?)

I am fairly new to VHDL (just graduated) and would greatly appreciate your help. Thanks :)