Evalueting problem condition in a verilog description

Good morning all !!

I allow myself to turn to you today after several to seek the solutions without success.

Indeed I am in a rather material project where it is necessary to set up a dating device using a CPLD card.

One of the functions to perform is the description of an SPI. It is a question of describing the SPI in such a way that we can have 4 states at the output (00, 01, 10 and 11) and this according to two inputs which are the CS and the CLOCK. For this, I use verilog as language.

The problem is that I cannot evaluate this condition in order to access the fourth state which would allow me to count down the 12 bits of data to be transmitted. I enclose the description and the timing diagram where I forced the entries.

Thank you all in advance.

Result

Here is the description

Code