how to write parametric priority if in verilog using generate? [closed]

I'm trying to create a synthesizable, parametrized priority encoder in Verilog. this is the code written in full:

assign out_winner = (|req_prio[3])? req_prio[3] : 
                    (|req_prio[2])?             req_prio[2] :
                    (|req_prio[1])?             req_prio[1] :
                                                in_req;

can anyone explain how do I convert it to parametric design where req_prio is [WIDTH-1:0] width? how do I use generate here?