VHDL for loop and if condition not working

I am using Altera fpga to do some calculation. therefore i need to access some values from integer arrays. i am using for loop to run through the array of integers and if condition to find the value whether it is in the array (array sta ), then i returns the index (array thetv) of that value,

Updated: I am using below code with HPS (soc-fpga), I got zero, I checked the output from altera monitor program's terminal via avalon memory mapping.

the code is given below. i checked and i do not get index value.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

S_up: process(clk_50)
variable i_num  : integer range 0 to 514 := 0;

variable thetv  : integer range -4194304 to 4194304 := 0;
--sta is an array of integer ranging from  -4194304 to 4194304 it has 512 values
variable sta  : int_array := (-4194304,...,0,... ,4194304);
--thet is an array of integer ranging from  -256 to 256 it has 512 values
variable thet  :int_array  := (-256,-255,254,...0...,230,...,255,256);
--above two arrays contains 512 elements which cannot put here.therefore i put it here in short form to understand.  
begin

if(reset_n = '1')then
      s <= to_signed(5,22); 
      elsif(rising_edge(clk_50)) then
  if clk_en = '1' then
     thetv := to_integer(signed(tta));
     for i_num in 0 to 511 loop

  --thetv  is integer  ranging from  -4194304 to 4194304 which was generated form tta of another process. tta updates and checked it. the if conditions are not running.

          if  (sta(i_num )  <  thetv  and  thetv  <  sta(i_num+1)) then
                        s <= to_signed(thet(i_num),22);
                    elsif(theta_int_inv = sta(i_num ) )then
                        s  <= to_signed(thet(i_num),22);
                    else
                        s  <= to_signed(0,22); 
              end if; 
      end loop;   
   end if;
  end if;
end process;
end rtl;