Verilog: if without else inside clocked always block creates register hold path

I recently came across Verilog code of this structure:

   reg flop_a;

   always @(posedge clk) begin
     if (reset)
       flop_a <= 1'b0;
     else if (some_condition)
       flop_a <= new_value;
   end

I would have explicitly coded a register's hold path, but leaving out the "else" condition and implying the hold path seems to work as well.

Why does this (safely) work? I can't find anything in the verilog IEEE spec's definition of an always block or if statement that defines this behavior.