IF Statement inside Case Statement is not working as expected in VHDL

I'm new to VHDL programming and stuck with the below operation:

           case fpga_dsi_csi_sel is
         when "10000100" => --csi0 enabled
            csi_mux_oe_n <= '0';
            dsi_mux_sel <= '1';
            csi_mux_csi0_csi2_sel <= '0';
            if (csi_mux_oe_n = '0') and (dsi_mux_sel = '1') and (csi_mux_csi0_csi2_sel = '0') then
                                    fpga_gpio_45 <= '0';
                                    fpga_gpio_45 <= '1';
                                    else fpga_gpio_45 <= '0';
            end if;    
         when "10000010" => --csi1 enabled
            csi_mux_oe_n <= '0';
            dsi_mux_sel <= '0';
            csi_mux_csi1_csi3_sel <= '1';
            if (csi_mux_oe_n = '0') and (dsi_mux_sel = '0') and (csi_mux_csi0_csi2_sel = '1') then
                        fpga_gpio_46 <= '0';
                        fpga_gpio_46 <= '1';
                        else fpga_gpio_46 <= '0';
            end if;

When csi0 is enabled ie. first case, first three operations are done sequentially. I want to keep a flag to make sure that the first 3 operations are executed so I have made a condition using If statement. If the first three statements are executed properly, fpga_gpio_45 should go high ie. 1 otherwise it should be 0.

When I execute the code, I can verify that first three statements are executed properly (because data flow is happening) but fpga_gpio_45 is not going high.

Can anyone pls help me here and let me know what is incorrect?

fpga_gpio_45 is defined as INOUT.