VHDL If condition

I have a an if condition in vhdl testbench. This if condition is working on false cases also

process(sigmoid_output_ready_tb, sigmoid_out_cuurent, finaloutput_trunc_top_tb)
  begin
   sigmoid_out_nxt <= sigmoid_out_cuurent;
  if ((sigmoid_output_ready_tb = '1') and (sigmoid_out_cuurent < 7840)) then
     rdataout(sigmoid_out_cuurent ) <= unsigned(finaloutput_trunc_top_tb);
     sigmoid_out_nxt <= sigmoid_out_cuurent + 1 ;


     end if;

if you can see in image my arrays location 1 is getting updated on falling edge of sigmoid_ready_tb signal. But as per if condition during next rising edge of sigmoid_ready_tb I need to update my location 1 of array. Does anyone know why it is behaving like this?enter image description here