I have a design I've implemented using vhdl that is triggered based on a clock that sends an input signal to one of 8 output channels based on the sel input and also another 2 bit input. The elaborated design shows a lot of nesting due to the many if-else statements. So, I'm curious as to if there's a way to alleviate the nesting using case statements or some other method. I'm unfamiliar with doing this using case statements because I have two inputs that determine the output channel. The code that I currently have is displayed below.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Inputs and outputs to entity
entity DSA_Worker is
Port ( DB_Select : in STD_LOGIC;
Atten : in STD_LOGIC_VECTOR ( 7 downto 0);
enable : in STD_LOGIC;
clk: in STD_LOGIC;
reset: in STD_LOGIC;
chip_select : in STD_LOGIC_VECTOR (1 downto 0);
DBA_TX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
DBA_TX2_DSA : out STD_LOGIC_VECTOR (7 downto 0);
DBA_RX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
DBA_RX2_DSA : out STD_LOGIC_VECTOR (7 downto 0);
DBB_TX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
DBB_TX2_DSA : out STD_LOGIC_VECTOR (7 downto 0);
DBB_RX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
DBB_RX2_DSA : out STD_LOGIC_VECTOR (7 downto 0));
end DSA_Worker;
architecture Behavioral of DSA_Worker is
begin
process(clk)
begin
if rising_edge(clk) then
--if reset is high, all outputs go to 0
if reset = '1'then
DBA_TX1_DSA <= (others =>'0');
DBA_TX2_DSA <= (others =>'0');
DBA_RX1_DSA <= (others =>'0');
DBA_RX2_DSA <= (others =>'0');
DBB_TX1_DSA <= (others =>'0');
DBB_TX2_DSA <= (others =>'0');
DBB_RX1_DSA <= (others =>'0');
DBB_RX2_DSA <= (others =>'0');
-- attenuation values sent to channels based on DB_select value(0/1) and chip select value
--DB_select - 0 is for DB-A and 1 for DB- B and chip_select determines the channel
elsif enable = '1'then
if(DB_Select='0' and chip_select = "00") then -- attenuation value sent to first channel
DBA_TX1_DSA(0) <= Atten(0);
DBA_TX1_DSA(1) <= Atten(1);
DBA_TX1_DSA(2) <= Atten(2);
DBA_TX1_DSA(3) <= Atten(3);
DBA_TX1_DSA(4) <= Atten(4);
DBA_TX1_DSA(5) <= Atten(5);
elsif (DB_Select='0' and chip_select = "01") then
DBA_TX2_DSA(0) <= Atten(0);
DBA_TX2_DSA(1) <= Atten(1);
DBA_TX2_DSA(2) <= Atten(2);
DBA_TX2_DSA(3) <= Atten(3);
DBA_TX2_DSA(4) <= Atten(4);
DBA_TX2_DSA(5) <= Atten(5);
elsif (DB_Select='0' and chip_select = "10") then
DBA_RX1_DSA(0) <= Atten(0);
DBA_RX1_DSA(1) <= Atten(1);
DBA_RX1_DSA(2) <= Atten(2);
DBA_RX1_DSA(3) <= Atten(3);
DBA_RX1_DSA(4) <= Atten(4);
DBA_RX1_DSA(5) <= Atten(5);
elsif (DB_Select='0' and chip_select = "11") then
DBA_RX2_DSA(0) <= Atten(0);
DBA_RX2_DSA(1) <= Atten(1);
DBA_RX2_DSA(2) <= Atten(2);
DBA_RX2_DSA(3) <= Atten(3);
DBA_RX2_DSA(4) <= Atten(4);
DBA_RX2_DSA(5) <= Atten(5);
-- Attenuation values being set for DB-B
elsif (DB_Select='1' and chip_select = "00") then
DBB_TX1_DSA(0) <= Atten(0);
DBB_TX1_DSA(1) <= Atten(1);
DBB_TX1_DSA(2) <= Atten(2);
DBB_TX1_DSA(3) <= Atten(3);
DBB_TX1_DSA(4) <= Atten(4);
DBB_TX1_DSA(5) <= Atten(5);
elsif (DB_Select='1' and chip_select = "01") then
DBB_TX2_DSA(0) <= Atten(0);
DBB_TX2_DSA(1) <= Atten(1);
DBB_TX2_DSA(2) <= Atten(2);
DBB_TX2_DSA(3) <= Atten(3);
DBB_TX2_DSA(4) <= Atten(4);
DBB_TX2_DSA(5) <= Atten(5);
elsif (DB_Select='1' and chip_select = "10") then
DBB_RX1_DSA(0) <= Atten(0);
DBB_RX1_DSA(1) <= Atten(1);
DBB_RX1_DSA(2) <= Atten(2);
DBB_RX1_DSA(3) <= Atten(3);
DBB_RX1_DSA(4) <= Atten(4);
DBB_RX1_DSA(5) <= Atten(5);
else
DBB_RX2_DSA(0) <= Atten(0);
DBB_RX2_DSA(1) <= Atten(1);
DBB_RX2_DSA(2) <= Atten(2);
DBB_RX2_DSA(3) <= Atten(3);
DBB_RX2_DSA(4) <= Atten(4);
DBB_RX2_DSA(5) <= Atten(5);
end if;
end if;
end if;
end process;
end Behavioral;
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