How can I use Verilog defines in an if-else statemnets

I have a Verilog define like this:

`define NUM_BANKS 4

and if want to use it in the following code:

if (`NUM_BANKS > 1)
  do something ..
else
  do something else ..

Lint tool is complaining that this expression is going to always be evaluated to true. How to fix this? I'd appreciate your help!

Thanks, Mohsen