always block if statement not working in verilog

My problem is that when i run this code the value of sb (initially at 0) stays at 0 even though it should change to 1. the starting value of irsg is 1 so negedge occurs first. If i comment out the negctr conditional at the posedge, it works correctly. what is going wrong when i use the negctr conditional statement?

always @(posedge irsg) begin

  if((c2>=sbl) &&(c2<=sbu))
    begin 

      if(negctr == 4'b0001)

      begin sb<=1'b1;end 
      else
       begin sb<=1'b0;
         end
    end

end //always

always @(negedge irsg) begin if (negctr==4'b1101) begin negctr<=4'b0001; end else begin negctr<=negctr+4'b0001;end

end