SystemVerilog 'if' statement inside always_comb 'not purely combinational logic' error

I'm confused! And a bit frustrated. I've spent quite a lot of time working on some SystemVerilog in Modelsim. I got it to a certain stage where I could test it on my hardware however compiling in Quartus was unsuccessful. I did understand this may happen but in this case my errors don't seem to make sense.

The code below is inside an always_comb block. When I compile I get the following error:

Error (10166): SystemVerilog RTL Coding error at fifo_interface.sv(80): always_comb construct does not infer purely combinational logic.

I really don't understand this. This is the code, it's just a mux.

always_comb
    if(fifo_select == 0)
    begin
        fifo0_data_in = data_in;
        fifo0_in_clk = in_clk;
        fifo0_in_dn = in_dn;
        in_rdy = fifo0_in_rdy;

        fifo1_in_clk = 0;   //Prevent 'in_clk' entering fifo1
    end

    else
    begin
        if(fifo_select == 1)
        begin
            fifo1_data_in = data_in;
            fifo1_in_dn = in_dn;
            fifo1_in_clk = in_clk;
            in_rdy = fifo1_in_rdy;

            fifo0_in_clk = 0;   //Prevent 'in_clk' entering fifo0
        end 
    end
end

When I change the block to type 'always' Modelsim will act strangely. It will break in the code or will crash altogether with the exit code 211. Changing the type back to 'always_comb' does not fix the issue and so I have to restart modelsim to successfully simulate the HDL.

I'm interested to know what the source of the error is?

Thanks for any help.