Verilog: Applications of using ! vs ~ in loop conditions

First post, couldn't find this anywhere on here (hoping that's true!).

I have been noticing that various resources (course notes vs. online resources) tend to use either the logical operator !, or the reduction operator ~ within the condition of an if statement.

For example, using this with an active-low reset:

if(!reset)

//reset statements, etc.

or

if(~reset)

//reset statements, etc.

I believe they both essentially give the same simulation result, thanks to knowing that the reset SHOULD/WOULD be a 1-bit binary input of 1 or 0. I understand that this may change if the condition were a multiple bit value.

Would there be any application benefit of selecting one over the other? Any examples someone could provide? What would be the changes with respect to synthesis? Simulation? Thanks in advance!