i have a couple of errors in my VHDL code, Can anyone see where I might be going wrong?

I am trying to take the 8 MSBs out of a 16-bit binary number and trying input it into an 8-bit adder. But I am getting a couple of errors that I don't understand. My code is as follows.

'''
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;


entity SegmentMethod is
    Port ( Ao : in UNSIGNED (15 downto 0);
           Bo : in UNSIGNED (15 downto 0);
           Co : out UNSIGNED (31 downto 0));
end SegmentMethod;

architecture Behavioral of SegmentMethod is

component Ripple_Adder
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (31 downto 0);
Cout : out STD_LOGIC);
end component;

signal z :STD_LOGIC_VECTOR (31 downto 0);
signal Ci: UNSIGNED (31 downto 0) := "00000000000000000000000000000000";
signal i :STD_LOGIC;
signal j :STD_LOGIC := '0';
signal Ai, Bi: STD_LOGIC_VECTOR (15 downto 0);

begin

--seg :process (A, B, z, i, Ai, Bi)
--begin
if (Ao'LENGTH >8) then
     Ai <= std_logic_vector(unsigned(Ao) sll (Ao'LENGTH -8));
else
     Bi <= std_logic_vector(unsigned(Bo) sll (Bo'LENGTH -8));
end if;


 A: Ripple_Adder port map (Ai,Bi ,j=>Cin ,z=>S ,i=>Cout );
 Ci <= Ci + unsigned(Z);
 Co <= Ci sll 8;
--end process seg;




end Behavioral;
'''

The two errors are in the "if" , "else" and "then" statements and The second one asks me to use formal/explicit port connection in the "port map" line ( A: Ripple_Adder port map (Ai,Bi ,j=>Cin ,z=>S ,i=>Cout );) . I am relatively new to VHDL (as you might have seen from my coding skills). I hope someone can help me out with this.

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