VHDL conditional type generation (flavor of FW)

I'm doing a DIY project with robots with different sensors. So I'm trying to have the maximum common code for all of them and here I get to the question:

it's possible to do something like if..generate in the packages? the next code is wrong but it's for illustrate what would be the best way to do it:

constant robo_type : integer := 1;

-- 6 legs, motors with encoders
6_legs_2_parts : if robo_type = 0 generate
    type leg_sens is record
        angle1 is array (5 downto 0) of integer range 0 to 1000;
        angle2 is array (5 downto 0) of integer range 0 to 1000;
    end record;
end generate;

-- 6 legs, motors with encoders
6_legs_3_parts : if robo_type = 1 generate
    type leg_sens is record
        angle1 is array (5 downto 0) of integer range 0 to 1000;
        angle2 is array (5 downto 0) of integer range 0 to 1000;
        angle3 is array (5 downto 0) of integer range 0 to 1000;
    end record;
end generate;

-- 4 legs motors, encoders & current
4_legs_2_parts : if robo_type = 2 generate
    type leg_sens is record
        angle1 is array (3 downto 0) of integer range 0 to 1000;
        angle2 is array (3 downto 0) of integer range 0 to 1000;
        amp1 is array (3 downto 0) of integer range 0 to 100;
        amp2 is array (3 downto 0) of integer range 0 to 1000;
    end record;
end generate;

Now I use something like this, and relay in that the compiler will optimize what I'm not using

-- generic leg_sens for all robots
constant numAngles : integer := 4;

type leg_sens is record
    angle1 is array (numAngles -1 downto 0) of integer range 0 to 1000;
    angle2 is array (numAngles -1 downto 0) of integer range 0 to 1000;
    angle3 is array (numAngles -1 downto 0) of integer range 0 to 1000;
    amp1 is array (numAngles -1 downto 0) of integer range 0 to 100;
    amp2 is array (numAngles -1 downto 0) of integer range 0 to 100;
    amp3 is array (numAngles -1 downto 0) of integer range 0 to 100;
end record;

I found this: https://electronics.stackexchange.com/questions/237770/vhdl-if-generate-in-the-preamble-is-it-possible but it isn't what I'm looking for.

So, I'm looking if it's possible to do conditionals inside the packages, I didn't found anything on the IEEE Standard VHDL Language Reference Manual (IEEE Std 1076™-2008)

Thanks