For loops in Verilog Module

I am trying to code an if-statement inside a for-loop in a Verilog module. I have two set conditions, if they are met then the for loop will run the variable 'Address'. But after simulating, the for-loop stays on a single iteration throughout the remainder of the simulation. I have tried isolating the for-loop and running it on its own, but the results appear to be the same. The goal is to have variable 'Address' run from 0 through 7 when the conditions are met, and pause when the conditions are not met.

        integer i=0;
        
        
        always@(enable,readwrite)
            begin
                for(i=0; i<8; i=i+1)
                   if (enable)
                        if (~readwrite)
                            Address[2:0] = i;
                        else
                            Address = Address;
            end