SystemVerilog, if-statements order inside an always_comb block

I am new to SystemVerilog and I would like to know how multiple assignments to the same signal are handled inside an always_comb block.

I am analyzing an FSM written by someonelse and I don't understand which would be the next state (signal named "ctrl_fsm_ns") if all the if-statements are true. Searching on google, I found out that here blocking assignments are used, so I expect that the last if-statement will decide the next state (so it is like a certain priority is assigned to each if-statement). But what if inside each if-block different signals are asserted? They will be all asserted even if the next state will be the last one, for example?

Here is the piece of code I don't understand.

always_comb
begin
  ...
  unique case (ctrl_fsm_cs)
   ...
   FIRST_FETCH:
   begin
    is_decoding_o = 1'b0;
    // Stall because of IF miss
    if ((id_ready_i == 1'b1) )
    begin
      ctrl_fsm_ns = DECODE;
    end

    // handle interrupts
    if (irq_req_ctrl_i & irq_enable_int) begin
      // This assumes that the pipeline is always flushed before
      // going to sleep.
      ctrl_fsm_ns = IRQ_TAKEN_IF;
      halt_if_o   = 1'b1;
      halt_id_o   = 1'b1;
    end

    if ((debug_req_pending || trigger_match_i) & (~debug_mode_q))
    begin
      ctrl_fsm_ns = DBG_TAKEN_IF;
      halt_if_o   = 1'b1;
      halt_id_o   = 1'b1;
    end

   end