The generate if condition must be a constant expression

I am trying to create an Immediate Generator for RISC-V assembly but I have encountered with if statement. Here is my code in Verilog:

module signextend(in, out, sel);
    parameter nin = 32;
    parameter nout = 32;
    input [nin-1:nin-25] in;
    input [2:0] sel;
    output [nout-1:0] out;
    
    if (sel == 3'b000)
        begin
            assign out[19:0] = in[31:12];
            assign out[31:20] = {12{in[31]}};
        end
    else if (sel == 3'b001) 
        begin
            assign out[11:0] = in[31:20];
            assign out[31:12] = {20{in[31]}};
        end
    else if (sel == 3'b010)
        begin
            assign out[4:0] = in[24:20];
            assign out[31:5] = 0;
        end
    else if (sel == 3'b011)
        begin
            assign out[3:0] = in[11:8];
            assign out[4:9] = in[30:25];
            assign out[10] = in[7];
            assign out[11] = in[31];
            assign out[31:12] = {20{in[31]}};
        end
    else if (sel == 3'b100)
        begin
            assign out[4:0] = in[11:7];
            assign out[11:5] = in[31:25];
            assign out[31:12] = {20{in[31]}};
        end
    else if (sel == 3'b101)
        begin
            assign out[9:0] = in[21:30];
            assign out[10] = in[20];
            assign out[18:11] = in[19:12];
            assign out[19] = in[31];
            assign out[31:20] = {12{in[31]}};
        end 
    else 
        assign out = 32'hxxxx;  
endmodule

The problem exists in each if statement: The generate if condition must be a constant expression.